Digital Fundamentals

 

1. Explain full subtractor and construct full subtractor using half subtractors.

2. Sate and prove DeMorgan Theorem.

3. Simplify the following Boolean functions to a minimum numbers of literals. 1. x + x’y 2. x (x’+y) 3.

x’y’z + x’yz + xy’ 4. xy + x’z +yz

4. With a neat block diagram explain the function of encoder. Explain priority encoder?

5. Explain T Flipflop with Excitation Table. Implement T flip flop using SR flip flop.

6. Design synchronous counter for sequence: 0134570 using T flip-flop.

7. Differentiate the Asynchronous counter and Synchronous counter. Explain 3- bit up/down

Asynchronous counter in detail.

8. Write short note on Programmable Logic Arrays.

9. Compare the Following in every aspect: TTL and CMOS

10. Explain working of master-slave JK flip-flop with necessary logic diagram, state equation and

state diagram.

11. How to generate 8x1 MUX using 4x1 MUX.

12. Derive and draw logic circuit for BCD to Excess-3 Code converter.

13. Simply Boolean function for F(W,X,Y,Z) = ( 0, 1, 2, 4 ,5 ,6 ,8, 9, 12, 13, 14)

14. Generate AND, OR, NOT, EXOR and EX-NOR gate using NAND as a universal gate

15. Draw logic circuit of Full Adder and Full Subtractor with truth table.

16. Simply Boolean Function : F=A'B'C+A'BC+AB'

17. Draw logic circuit for 2-Bit Magnitude Comparator

18. Draw and explain Ring counter

19. Implement the following Boolean functions with a multiplexer and Decoder. F(w, x, y, z) = Σ (2, 3,

5, 6, 11, 14, 15)

20. Explain Serial Transfer w.r.t Shift Register with suitable example.

21. Simplify the following Boolean function by means of the Tabulation Method. F(A,B,C,D) =

∑(1,2,3,5,6,7,8,9,12,13,15)

22. Reduce the expression in SOP and POS form using K-map. F(A,B,C,D) = ∑m (1,5,6,12,13,14) +

d(2,4)

23. With necessary sketch explain Bidirectional Shift Register with parallel load

24. Implement the given function using 8 X 1 Multiplexer F (A,B,C,D) = ∑m (0,1,2,3,5,8,9,11,14)

25. Minimize following Boolean function using K-map & design the simplified function using logic

gates. F = ∑ m(1, 2, 4, 6, 7, 11, 15) + ∑ d(0, 3)

26. Design 3-bit parity generator circuit using even parity bit.

27. Explain Excess-3 code and Gray Code.